1. Technical Field of the Invention
The present invention relates to magnetic random access memories, and more particularly to a magnetic random access memory array architecture wherein the bit lines and/or the word lines are used not only during the element read operation but also to select the write bit line(s) and/or write digit line(s) during the element write operation.
2. Description of Related Art
A magnetic random access memory (MRAM) element typically has a structure that includes a first and second magnetic layers which are separated by a non-magnetic layer. A magnetic vector in one of the two magnetic layers is magnetically fixed or pinned, while the magnetic vector of the other of the two magnetic layers is not fixed and thus its magnetization direction is free to be controlled and switched. Information is written to and read from the element as a logic “1” or a logic “0” (i.e., one or the other of two possible logic states) by changing the direction of the non-fixed magnetization vector in the other of the two magnetic layers. The differences in magnetization vector direction cause resistance variations within the element which can be measured. For example, the shifting of the magnetization vector direction can represent two different resistances or potentials, which are then read by the memory circuit as either a logic “1” or a logic “0.” The detection of these resistance or potential differences due to shifting magnetization vector direction allows information to be written to and read from the MRAM element.
Reference is now made to FIGS. 1A and 1B wherein there are shown schematic diagrams of conventional MRAM elements 10. Each element includes a bit line 12 and a word line 14. The memory storing structure of the element 10 is referred to as a “magnetic tunnel junction” 16 (MTJ) which is represented in the schematic by a variable resistance and is physically composed of the first and second magnetic layers and the separating non-magnetic layer discussed above.
With reference to FIG. 1A, one end of this resistance is connected to the bit line 12. The other end of the resistance is connected to a conduction terminal of an access transistor 18. The access transistor 18 in the illustrated element 10 is an n-channel FET with its source conduction terminal connected to ground and its drain conduction terminal connected to the other end of the resistance. The gate terminal of the access transistor 18 is connected to the word line 14.
With reference to FIG. 1B, one end of this resistance is connected to a reference voltage (for example, a ground reference). The other end of the resistance is connected to a conduction terminal of an access transistor 18. The access transistor 18 in the illustrated element 10 is an n-channel FET with its source conduction terminal connected to the bit line 12 and its drain conduction terminal connected to the other end of the resistance. The gate terminal of the access transistor 18 is connected to the word line 14.
In either of the embodiments of FIGS. 1A and 1B, a write bit line 22 (WBL) and a write digit line 24 (WDL) for the element 10 intersect at the magnetic tunnel junction 14. These lines 22 and 24 selectively carry currents and thus each selectively create a magnetic flux proximate to the magnetic tunnel junction 16. The magnetic fields induced by current flow in the lines 22 and 24 can be used to set the non-fixed direction of the magnetic vector within the magnetic tunnel junction 16. As discussed above, the setting of this direction affects the resistance of the magnetic tunnel junction 16. By selectively choosing the current flow in the lines 22 and 24, one can program the magnetic tunnel junction 16, through its varying resistance, to store either one of two logic states: a logic “1” or a logic “0.” It is recognized, however, that the current in both the lines 22 and 24 must be of a certain magnitude in order to effectively control the non-fixed direction of the magnetic vector within the magnetic tunnel junction 16. It is accordingly imperative that sufficient current be made available in both lines 22 and 24 in order to write information into the element 10.
Reference is now made to FIG. 2 wherein there is shown a block diagram of a conventional MRAM memory array 50. The array 50 includes a plurality of individual MRAM elements 10 (of any suitable type including either of those shown in FIGS. 1A and 1B) arranged in a N×M array format. Each column 52 of elements 10 in the array 50 includes a bit line 12 and a write bit line 22. Each row 54 of elements 10 in the array 50 includes a word line 14 and a write digit line 24. Selection of a write digit line 24 and write bit line 22, along with the application of appropriate currents thereto, results in the writing of an information bit to the element 10 in the array 50 where the selected write digit line and write bit line intersect. Selection of a bit line 12 and a word line 14 turns on the access transistor 18 located at the intersection of the selected bit line(s) and word line, and causes a current to flow through the magnetic tunnel junction 16 resistance whose magnitude is dependent on the programmed non-fixed direction of the magnetic vector within the magnetic tunnel junction. A sense amplifier (not shown) that is connected to each selected bit line 12 measures the current flowing in the bit line, as affected by the current flowing through the magnetic tunnel junction 16 resistance, in order to “read” the logic state of the element 10.
The write bit lines 22 and write digit lines 24 which extend across the columns and rows, respectively, of the array 50 are coupled between first and second reference voltages (for example, a positive voltage and ground) through a plurality of selection transistors 62 and 64. A column decoder 72 receives address information over an address bus 58 and selects a plurality of columns in the array for the address and applies control signals, as dictated by the data to be written to the array, to the selection transistors 62 associated with those columns. Similarly, a row decoder 74 receives address information over an address bus 68 perhaps the same as bus 58) and selects a row of the array for the address and applies a control signal to the selection transistor 64 associated with that row. Responsive to the selection signals appropriate currents are generated (or not generated) in the write bit lines 22 and write digit line 24 at the addressed elements 10 in the memory array to program the magnetic vectors of the addressed elements to store the data to be written to the array.